eext-kap1bala

eext-kap1bala/fill-with-vias

为PCB批量放置过孔,并删除违反DRC的过孔

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Apache License 2.0

This project is a PCB design tool that automatically places vias in bulk and removes any that violate design rule checks (DRC). It is designed for PCB designers and engineers who need to efficiently populate their boards with vias while ensuring compliance with DRC standards.

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